1. Technical Field of the Invention
The present invention generally relates to switching systems used in communications networks. More particularly, and not by way of any limitation, the present invention is directed to a look-up table (LUT)-based arbitration (LTA) system and method for use in a network switch element.
2. Description of Related Art
Network communications technology is rapidly advancing in a direction in which the transmission speeds will continue to supersede the switching speeds. Accordingly, switching systems of the future will require the ability to accommodate data transfer rates in excess of 100 times what has been common until recently. For example, a switching system to be used in the core network (e.g., a core router) may have up to 512 input channels and 512 output channels, each with a data transmission rate of several gigabits per second. The ability to switch such high-speed traffic requires the use of advanced scheduling systems in conjunction with fast switching fabrics having very short time slots. Furthermore, it is expected that these concerns will become particularly acute in the deployment of the Next Generation Network (NGN) infrastructure where Quality of Service (QoS) will also be of critical importance.
Numerous approaches to implementing fast scheduling algorithms currently exist. As is well-known, these scheduling algorithms generally require the use of arbitration as a resolution mechanism among a plurality of units (e.g., servers associated with input and output ports of a network element) contending for a common resource, i.e., the bandwidth of a switching fabric, which units must establish appropriate traffic paths before data can be transported across the fabric. Since arbitration times can take a significant portion of a scheduling process, it is highly desirable to implement a faster arbitration scheme where massive throughput rates are required.
Known solutions for supporting fast arbitrations (i.e., where arbitration iterations can be executed in a few clock cycles) involve arbiters whose structure and logic are implemented in hardware. Such hardware implementations of round-robin arbiters (RRAS) and binary tree arbiters (BTAs) are exemplary. Whereas these solutions are generally adequate with respect to the state-of-the-art switching system architectures, certain deficiencies and shortcomings persist. First, the existing hardware arbiters are generally comprised of complex logic, requiring a rather large gate count and expensive implementation. Thus, their price/performance ratios are not entirely satisfactory. Further, although current hardware arbiters are typically faster than their software counterparts, their performance is still not acceptable for supporting the next-level switching performance.